Memory devices for a variety of computing systems are designed according to different standards. For example, different standards exist for memory devices primarily used in desktop systems and memory devices primarily used in low-power solutions.
Many memory devices are designed according to a Joint Electron Devices Engineering Council (JEDEC) standard. For example, many desktop and server systems use a double data rate (DDR)-based design. Typically these the systems are designed with a multi-drop memory bus to provide interconnection between system memory and a memory controller. Generally, these conventional DDR standards are referred to as “DDRx” standards.
In contrast, many low-power portable devices use memory devices in accordance with a low power DDR standard such as the current LPDDR2 standard according to JEDEC JESD 209-2E (published April 2009). Presently, a next generation LPDDR standard is being developed (referred to as LPDDR3) that will offer extensions to LPDDR2 to increase bandwidth. Generally, these low power standards are referred to as “LPDDRx” standards. Low-power-based memory designs differ from conventional DDR-based designs in various ways to enable operation at reduced power consumption levels. However, this can result in reduced speeds and lesser memory capacities.
The LPDDRx standards are designed for point-to-point low power solutions such as mobile phones, tablet computers, and other highly portable devices. Oftentimes, memory in these devices is implemented in a package-on-package (POP) package to enhance performance by providing the memory in close relation to a memory controller.
In contrast, conventional laptop/mobile platforms are designed with a multi-drop design, often with the memory not co-located with memory controller as in a POP package. As a result, significant signal integrity issues occur when using LPDDR-based memory in a multi-drop bus configuration such as a laptop computer, due to LPDDR command bus design limitations.